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mbm29lv160t -80/-90/-12 / mbm29lv160b -80/-90/-12 mbm29lv160t -80/-90/-12 /mbm29lv160b - 80/-90/-12 cover sheet data sheet (retired product) this product has been retired and is not recommended for new designs . availability of this document is retained for reference and historical purposes only. continuity of specifications there is no change to this data sheet as a result of offering the device as a spansi on product. any changes that have been made are the result of normal data sheet improvem ent and are noted in the document revision summary. for more information please contact your local sales office for additional information about spansion memory solutions. publication number mbm29lv160t/mbm29lv160b revision ds05-20846-7e issue date july 26, 2007
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september 2003 this document specifies spansion memory products that are now offered by both advanced micro devices and fujitsu. although the document is marked with the name of the company that originally developed the specification, these products will be offered to cu stomers of both amd and fujitsu. continuity of specifications there is no change to this datasheet as a result of offering the device as a spansion product. future routine revisions will occur when appropriate, and ch anges will be noted in a revision summary. continuity of ordering part numbers amd and fujitsu continue to support existing part numbers beginning with "am" and "mbm". to order these products, please use only the ordering part numbers listed in this document. for more information please contact your local amd or fujitsu sales office for additional information about spansion memory solutions. tm tm tm spansion flash memory data sheet tm
ds05-20846-7e fujitsu semiconductor data sheet retired product y ds05-20846-7e_july 26, 2007 flash memory cmos 16m (2m 8/1m 16) bit mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 general description the mbm29lv160t/b is a 16m-bit, 3.0 v-only flash memory organized as 2m bytes of 8 bits each or 1m words of 16 bits each. the mbm29lv160t/b is offered in a 48- pin tsop (1), 48-pin csop and 48-ball fbga packages. the device is designed to be programmed in-system with the standard system 3.0 v v cc supply. 12.0 v v pp and 5.0 v v cc are not required for write or erase operations. the device can also be reprogrammed in standard eprom programmers. the standard mbm29lv160t/b offers access times of 80 ns and 120 ns, allowing operation of high-speed microprocessors without wait states. to eliminate bus contention the device has separate chip enable (ce ), write enable (we ), and output enable (oe ) controls. the mbm29lv160t/b is pin and command set compatible with jedec standard e 2 proms. commands are written to the command register using standard microprocessor write timings. register contents serve as input to an internal state-machine which controls the erase and programming circuitry. write cycles also internally latch addresses and data needed for the programming and erase operations. reading data out of the device is similar to reading from 5.0 v and 12.0 v flash or eprom devices. the mbm29lv160t/b is pr ogrammed by executing the program command sequence. this will invoke the embedded program algorithm which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margins. typically, each sector can be programmed and verified in about 0.5 seconds. erase is accomplished by executing the erase comm and sequence. this will in voke the embedded erase algorithm which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. during erase, th e device automatically times the erase pulse widths and verifies proper cell margins. (continued) product line up part no. mbm29lv160t/160b ordering part no. v cc = 3.3 v -80 ? ? v cc = 3.0 v ?-90-12 max address access time (ns) 80 90 120 max ce access time (ns) 80 90 120 max oe access time (ns) 30 35 50 +0.3 v ?0.3 v +0.6 v ?0.3 v
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 5 (continued) any individual sector is typically erased and verified in 1.0 second. (if already preprogrammed.) the device also features a sector erase architecture. the sector mode allows each sector to be erased and reprogrammed without affecting other sectors. the mbm29lv160t/b is erased when shipped from the factory. the device features single 3.0 v power supply operation for both read and write functions. internally generated and regulated voltages are provided for the program and erase operations. a low v cc detector automatically inhibits write operations on the loss of power. the end of program or erase is detected by data polling of dq 7 , by the toggle bit feature on dq 6 , or the ry/by output pin. once the end of a program or erase cycle has been comleted, the device internally resets to the read mode. the mbm29lv160t/b also has a hardware reset pin. when this pin is driven low, execution of any embedded program algorithm or embedded erase algorithm is terminated. the internal state machine is then reset to the read mode. the reset pin may be tied to the system reset circuitry. therefore, if a system reset occurs during the embedded program algorithm or embedded erase algorithm, the device is automatically reset to the read mode and will have erroneous data stored in the address location s being programmed or erased. these locations need re-writing after the reset. resetting the device enables the system?s microprocessor to read the boot-up firmware from the flash memory. fujitsu?s flash technology combines years of flash me mory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. th e mbm29lv160t/b memory electrically erases all bits within a sector simultaneously via fowler-nordhiem tunneling. the bytes/words are programmed one byte/word at a time using the eprom programming mechanism of hot electron injection. features ? single 3.0 v read, program and erase minimizes system level power requirements compatible with jedec-standard commands uses same software commands as e 2 proms compatible with jedec-standard world-wide pinouts 48-pin tsop (1) (package suffix: pftn-normal bend type, pftr-reversed bend type) 48-pin csop (package suffix: pcv) 48-ball fbga (package suffix: pbt) minimum 100,000 program/erase cycles high performance 80 ns maximum access time sector erase architecture one 8k word, two 4k words, one 16k word, and thirty-one 32k words sectors in word mode one 16k byte, two 8k bytes, one 32k byte, and thirty-one 64k bytes sectors in byte mode any combination of sectors can be concurrently erased. also supports full chip erase boot code sector architecture t = top sector b = bottom sector embedded erase tm * algorithms automatically pre-programs and erases the chip or any sector embedded program tm * algorithms automatically programs and verifies data at specified address data polling and toggle bit feature for detection of program or erase cycle completion ready/busy output (ry/by ) hardware method for detection of program or erase cycle completion (continued)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 6 (continued) automatic sleep mode when addresses remain stable, automatically switches themselves to low power mode low v cc write inhibit 2.5 v erase suspend/resume suspends the erase operation to allow a read data and/or program in another sector within the same device sector protection hardware method disables any combination of sectors from program or erase operations sector protection set function by extended sector protect command fast programming function by extended command temporary sector unprotection temporary sector unpr otection via the reset pin in accordance with cfi (c ommon f lash memory i nterface) *: embedded erase tm and embedded program tm are trademarks of advanced micro devices, inc. packages 48-pin plastic tsop (1) (fpt-48p-m19) (fpt-48p-m20) 48-pin plastic csop 48-pin plastic fbga (lcc-48p-m03) (bga-48p-m13) marking side marking side
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 7 pin assignments (continued) normal bend tsop(1) (marking side) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 15 a 14 a 13 a 12 a 11 a 10 a 9 a 8 a 19 n.c. we reset n.c. n.c. ry/by a 18 a 17 a 7 a 6 a 5 a 4 a 3 a 2 a 1 a 16 byte v ss dq 15 /a -1 dq 7 dq 14 dq 6 dq 13 dq 5 dq 12 dq 4 v cc dq 11 dq 3 dq 10 dq 2 dq 9 dq 1 dq 8 dq 0 oe v ss ce a 0 (fpt-48p-m19) reverse bend (marking side) 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry/by n.c. n.c. reset we n.c. a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 /a -1 v ss byte a 16 (fpt-48p-m20)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 8 (continued) a1 b1 c1 d1 e1 f1 g1 h1 a2 b2 c2 d2 e2 f2 g2 h2 a3 b3 c3 d3 e3 f3 g3 h3 a4 b4 c4 d4 e4 f4 g4 h4 a5 b5 c5 d5 e5 f5 g5 h5 a6 b6 c6 d6 e6 f6 g6 h6 marking side (top view) fbga (bga-48p-m13) a1 a 3 a2 a 7 a3 ry/by a4 we a5 a 9 a6 a 13 b1 a 4 b2 a 17 b3 n.c. b4 reset b5 a 8 b6 a 12 c1 a 2 c2 a 6 c3 a 18 c4 n.c. c5 a 10 c6 a 14 d1 a 1 d2 a 5 d3 n.c. d4 a 19 d5 a 11 d6 a 15 e1 a 0 e2 dq 0 e3 dq 2 e4 dq 5 e5 dq 7 e6 a 16 f1 ce f2 dq 8 f3 dq 10 f4 dq 12 f5 dq 14 f6 byte g1 oe g2 dq 9 g3 dq 11 g4 v cc g5 dq 13 g6 dq 15 /a -1 h1 v ss h2 dq 1 h3 dq 3 h4 dq 4 h5 dq 6 h6 v ss (top view) csop-48 (lcc-48p-m03) a 1 a 2 a 3 a 4 a 5 a 6 a 7 a 17 a 18 ry / by n.c. n.c. reset we n.c. a 19 a 8 a 9 a 10 a 11 a 12 a 13 a 14 a 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 a 0 ce v ss oe dq 0 dq 8 dq 1 dq 9 dq 2 dq 10 dq 3 dq 11 v cc dq 4 dq 12 dq 5 dq 13 dq 6 dq 14 dq 7 dq 15 / a -1 v ss byte a 16
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 9 pin descriptions pin name function a 19 to a 0 , a -1 address inputs dq 15 to dq 0 data inputs/outputs ce chip enable oe output enable we write enable ry/by ready/busy output reset hardware reset pin/temporary sector unprotection byte selects 8-bit or 16-bit mode n.c. pin not connected internally v ss device ground v cc device power supply
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 10 block diagram logic symbol v ss v cc we ce a 19 to a 0 oe erase voltage generator dq 15 to dq 0 state control command register program voltage generator low v cc detector address latch x-decoder y-decoder cell matrix y-gating chip enable output enable logic data latch input/output buffers stb stb a -1 byte reset ry/by buffer ry/by timer for program/erase 20 a 19 to a 0 we ry/by oe ce a -1 dq 15 to dq 0 16 or 8 reset byte
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 11 device bus operation mbm29lv160t/b user bus operation table (byte = v ih ) legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see ? dc characteristics? for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see ?mbm29lv160t/b standard command definitions table?. *2 : refer to the section on sector protection. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. *4 : v cc = 3.3 v 10% *5 : it is also used for the extended sector protection. mbm29lv160t/b user bus operation table (byte = v il ) legend: l = v il , h = v ih , x = v il or v ih . = pulse input. see ? dc characteristics? for voltage levels. *1 : manufacturer and device codes may also be accessed via a command register write sequence. see ?mbm29lv160t/b standard command definitions table?. *2 : refer to the section on sector protection. *3 : we can be v il if oe is v il , oe at v ih initiates the write operations. *4 : v cc = 3.3 v 10% *5 : it is also used for the extended sector protection. operation ce oe we a 0 a 1 a 6 a 9 dq 15 to dq 0 reset auto-select manufacture code * 1 llhlllv id code h auto-select device code * 1 llhhllv id code h read * 3 llha 0 a 1 a 6 a 9 d out h standby h x x x x x x high-z h output disable l h h x x x x high-z h write (program/erase) l h l a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lv id lhlv id xh verify sector protection * 2, * 4 llhlhlv id code h temporary sector unprotection * 5 xxxxxxx x v id reset (hardware)/standby x x x x x x x high-z l operation ce oe we dq 15 /a -1 a 0 a 1 a 6 a 9 dq 15 to dq 0 reset auto-select manufacture code * 1 llh l lllv id code h auto-select device code * 1 llh l hllv id code h read * 3 llh a -1 a 0 a 1 a 6 a 9 d out h standby h x x x x x x x high-z h output disable l h h x x x x x high-z h write (program/erase) l h l a -1 a 0 a 1 a 6 a 9 d in h enable sector protection * 2, * 4 lv id llhlv id xh verify sector protection * 2, * 4 llh l lhlv id code h temporary sector unprotection * 5 xxxxxxxx x v id reset (hardware)/standby x x x x x x x x high-z l
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 12 mbm29lv160t/b standard command definitions table *1: address bits a 19 to a 11 = x = ?h? or ?l? for all address commands except or program address (pa) and sector address (sa). *2: bus operations are defined in ?mbm29lv160t/b user bus operation tables (byte = v ih and byte = v il )?. *3: ra= address of the memory location to be read. pa = address of the memory locati on to be programmed. addresse s are latched on the falling edge of the we pulse. sa= address of the sector to be erased. the combination of a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 will uniquely select any sector. *4: rd= data read from location ra during read operation. pd= data to be programmed at location pa. data is latched on the rising edge of we . *5: the system should generate the following address patterns: word mode: 555h or 2aah to addresses a 10 to a 0 byte mode: aaah or 555h to addresses a 10 to a -1 *6: both read/reset commands are functionally equivalent, resetting the device to the read mode. note: the command combinations not described in ?mbm29lv160t/b standard command definitions? and ?mbm29lv160t/b extended comm and definitions? are illegal. command sequence * 1, * 2, * 3, * 5 bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read/write cycle fifth bus write cycle sixth bus write cycle addr data addr data addr data addr data addr data addr data read/reset * 6 word /byte 1 xxxh f0h ? ????????? read/reset * 6 word 3 555h aah 2aah 55h 555h f0h ra rd ? ? ? ? byte aaah 555h aaah autoselect word 3 555h aah 2aah 55h 555h 90h?????? byte aaah 555h aaah byte/word program * 3, * 4 word 4 555h aah 2aah 55h 555h a0h pa pd ? ? ? ? byte aaah 555h aaah chip erase word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h byte aaah 555h aaah aaah 555h aah sector erase * 3 word 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h byte aaah 555h aaah aaah 555h sector erase suspend word /byte 1 xxxh b0h ? ????????? sector erase resume word /byte 1 xxxh 30h ? ?????????
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 13 mbm29lv160t/b extended command definitions table spa : sector address to be protected. set sector address (sa) and (a 6 , a 1 , a 0 ) = (0, 1, 0). sd : sector protection verify data. output 01h at protecte d sector addresses and output 00h at unprotected sector addresses. *1 : this command is valid during fast mode. *2 : the valid addresses are a 6 to a 0 . the other addresses are ?don?t care?. *3 : this command is valid while v id = reset . *4 : the data ?00h? is also acceptable. command sequence bus write cycles req'd first bus write cycle second bus write cycle third bus write cycle fourth bus read cycle addr data addr data addr data addr data set to fast mode word 3 555h aah 2aah 55h 555h 20h ? ? byte aaah 555h aaah fast program * 1 word 2 xxxh a0h pa pd ? ? ? ? byte xxxh reset from fast mode * 1 word 2 xxxh 90h xxxh f0h * 4 ???? byte xxxh xxxh query command * 2 word 2 55h 98h ? ? ? ? ? ? byte aah extended sector protect * 3 word 4 xxxh 60h spa 60h spa 40h spa sd byte
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 14 mbm29lv160t/b sector protection verify autoselect code table *1: a -1 is for byte mode. at byte mode, dq 14 to dq 8 are high-z and dq 15 is a- 1 , the lowest address. *2: outputs 01h at protected sector addresses and outputs 00h at unprotected sector addresses. extended autoselect code table (b): byte mode (w): word mode hi-z : high-z * : at byte mode, dq 14 to dq 8 are high-z and dq 15 is a- 1 , the lowest address. type a 19 to a 12 a 6 a 1 a 0 a -1 * 1 code (hex) manufacture?s code x v il v il v il v il 04h device code mbm29lv160t byte xv il v il v ih v il c4h word x 22c4h mbm29lv160b byte xv il v il v ih v il 49h word x 2249h sector protection sector addresses v il v ih v il v il 01h* 2 type code dq 15 dq 14 dq 13 dq 12 dq 11 dq 10 dq 9 dq 8 dq 7 dq 6 dq 5 dq 4 dq 3 dq 2 dq 1 dq 0 manufacture?s code 04h a -1 /00000000 00000100 device code mbm29lv160t (b)* c4h a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z11000100 (w) 22c4h 00100010 11000100 mbm29lv160b (b)* 49h a -1 hi-zhi-zhi-zhi-zhi-zhi-zhi-z01001001 (w) 2249h 00100010 01001001 sector protection 01h a -1 /00000000 00000001
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 15 flexible sector-erase architecture one 8k word, two 4k words, one 16k word, and thirty-one 32k words sectors in word mode. one 16k byte, two 8k bytes, one 32k byte, and thirty-one 64k bytes sectors in byte mode. individual-sector, multiple-sec tor, or bulk-erase capability. individual or multiple-sector protection is user definable. mbm29lv160t top boot sector architecture sector sector size ( 8) address range ( 16) address range sa0 64 kbytes or 32 kwords 00000h to 0ffffh 00000h to 07fffh sa1 64 kbytes or 32 kwords 10000h to 1ffffh 08000h to 0ffffh sa2 64 kbytes or 32 kwords 20000h to 2ffffh 10000h to 17fffh sa3 64 kbytes or 32 kwords 30000h to 3ffffh 18000h to 1ffffh sa4 64 kbytes or 32 kwords 40000h to 4ffffh 20000h to 27fffh sa5 64 kbytes or 32 kwords 50000h to 5ffffh 28000h to 2ffffh sa6 64 kbytes or 32 kwords 60000h to 6ffffh 30000h to 37fffh sa7 64 kbytes or 32 kwords 70000h to 7ffffh 38000h to 3ffffh sa8 64 kbytes or 32 kwords 80000h to 8ffffh 40000h to 47fffh sa9 64 kbytes or 32 kwords 90000h to 9ffffh 48000h to 4ffffh sa10 64 kbytes or 32 kwords a0000h to affffh 50000h to 57fffh sa11 64 kbytes or 32 kwords b0000h to bffffh 58000h to 5ffffh sa12 64 kbytes or 32 kwords c0000h to cffffh 60000h to 67fffh sa13 64 kbytes or 32 kwords d0000h to dffffh 68000h to 6ffffh sa14 64 kbytes or 32 kwords e0000h to effffh 70000h to 77fffh sa15 64 kbytes or 32 kwords f0000h to fffffh 78000h to 7ffffh sa16 64 kbytes or 32 kwords 100000h to 10ffffh 80000h to 87fffh sa17 64 kbytes or 32 kwords 110000h to 11ffffh 88000h to 8ffffh sa18 64 kbytes or 32 kwords 120000h to 12ffffh 90000h to 97fffh sa19 64 kbytes or 32 kwords 130000h to 13ffffh 98000h to 9ffffh sa20 64 kbytes or 32 kwords 140000h to 14ffffh a0000h to a7fffh sa21 64 kbytes or 32 kwords 150000h to 15ffffh a8000h to affffh sa22 64 kbytes or 32 kwords 160000h to 16ffffh b0000h to b7fffh sa23 64 kbytes or 32 kwords 170000h to 17ffffh b8000h to bffffh sa24 64 kbytes or 32 kwords 180000h to 18ffffh c0000h to c7fffh sa25 64 kbytes or 32 kwords 190000h to 19ffffh c8000h to cffffh sa26 64 kbytes or 32 kwords 1a0000h to 1affffh d0000h to d7fffh sa27 64 kbytes or 32 kwords 1b0000h to 1bffffh d8000h to dffffh sa28 64 kbytes or 32 kwords 1c0000h to 1cffffh e0000h to e7fffh sa29 64 kbytes or 32 kwords 1d0000h to 1dffffh e8000h to effffh sa30 64 kbytes or 32 kwords 1e0000h to 1effffh f0000h to f7fffh sa31 32 kbytes or 16 kwords 1f0000h to 1f7fffh f8000h to fbfffh sa32 8 kbytes or 4 kwords 1f8000h to 1f9fffh fc000h to fcfffh sa33 8 kbytes or 4 kwords 1fa000h to 1fbfffh fd000h to fdfffh sa34 16 kbytes or 8 kwords 1fc000h to 1fffffh fe000h to fffffh
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 16 mbm29lv160b bottom boot sector architecture sector sector size ( 8) address range ( 16) address range sa0 16 kbytes or 8 kwords 00000h to 03fffh 00000h to 01fffh sa1 8 kbytes or 4 kwords 04000h to 05fffh 02000h to 02fffh sa2 8 kbytes or 4 kwords 06000h to 07fffh 03000h to 03fffh sa3 32 kbytes or 16 kwords 08000h to 0ffffh 04000h to 07fffh sa4 64 kbytes or 32 kwords 10000h to 1ffffh 08000h to 0ffffh sa5 64 kbytes or 32 kwords 20000h to 2ffffh 10000h to 17fffh sa6 64 kbytes or 32 kwords 30000h to 3ffffh 18000h to 1ffffh sa7 64 kbytes or 32 kwords 40000h to 4ffffh 20000h to 27fffh sa8 64 kbytes or 32 kwords 50000h to 5ffffh 28000h to 2ffffh sa9 64 kbytes or 32 kwords 60000h to 6ffffh 30000h to 37fffh sa10 64 kbytes or 32 kwords 70000h to 7ffffh 38000h to 3ffffh sa11 64 kbytes or 32 kwords 80000h to 8ffffh 40000h to 47fffh sa12 64 kbytes or 32 kwords 90000h to 9ffffh 48000h to 4ffffh sa13 64 kbytes or 32 kwords a0000h to affffh 50000h to 57fffh sa14 64 kbytes or 32 kwords b0000h to bffffh 58000h to 5ffffh sa15 64 kbytes or 32 kwords c0000h to cffffh 60000h to 67fffh sa16 64 kbytes or 32 kwords d0000h to dffffh 68000h to 6ffffh sa17 64 kbytes or 32 kwords e0000h to effffh 70000h to 77fffh sa18 64 kbytes or 32 kwords f0000h to fffffh 78000h to 7ffffh sa19 64 kbytes or 32 kwords 100000h to 10ffffh 80000h to 87fffh sa20 64 kbytes or 32 kwords 110000h to 11ffffh 88000h to 8ffffh sa21 64 kbytes or 32 kwords 120000h to 12ffffh 90000h to 97fffh sa22 64 kbytes or 32 kwords 130000h to 13ffffh 98000h to 9ffffh sa23 64 kbytes or 32 kwords 140000h to 14ffffh a0000h to a7fffh sa24 64 kbytes or 32 kwords 150000h to 15ffffh a8000h to affffh sa25 64 kbytes or 32 kwords 160000h to 16ffffh b0000h to b7fffh sa26 64 kbytes or 32 kwords 170000h to 17ffffh b8000h to bffffh sa27 64 kbytes or 32 kwords 180000h to 18ffffh c0000h to c7fffh sa28 64 kbytes or 32 kwords 190000h to 19ffffh c8000h to cffffh sa29 64 kbytes or 32 kwords 1a0000h to 1affffh d0000h to d7fffh sa30 64 kbytes or 32 kwords 1b0000h to 1bffffh d8000h to dffffh sa31 64 kbytes or 32 kwords 1c0000h to 1cffffh e0000h to e7fffh sa32 64 kbytes or 32 kwords 1d0000h to 1dffffh e8000h to effffh sa33 64 kbytes or 32 kwords 1e0000h to 1effffh f0000h to f7fffh sa34 64 kbytes or 32 kwords 1f0000h to 1fffffh f8000h to fffffh
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 17 sector address table (mbm29lv160t) sector address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ( 8) address range ( 16) address range sa0 0 0 0 0 0 x x x 00000h to 0ffffh 00000h to 07fffh sa1 0 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa2 0 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa3 0 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa4 0 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa5 0 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa6 0 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa7 0 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa8 0 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa9 0 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa10 0 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa11 0 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa12 0 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa13 0 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa14 0 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa15 0 1 1 1 1 x x x f0000h to fffffh 78000h to 7ffffh sa16 1 0 0 0 0 x x x 100000h to 10ffffh 80000h to 87fffh sa17 1 0 0 0 1 x x x 110000h to 11ffffh 88000h to 8ffffh sa18 1 0 0 1 0 x x x 120000h to 12ffffh 90000h to 97fffh sa19 1 0 0 1 1 x x x 130000h to 13ffffh 98000h to 9ffffh sa20 1 0 1 0 0 x x x 140000h to 14ffffh a0000h to a7fffh sa21 1 0 1 0 1 x x x 150000h to 15ffffh a8000h to affffh sa22 1 0 1 1 0 x x x 160000h to 16ffffh b0000h to b7fffh sa23 1 0 1 1 1 x x x 170000h to 17ffffh b8000h to bffffh sa24 1 1 0 0 0 x x x 180000h to 18ffffh c0000h to c7fffh sa25 1 1 0 0 1 x x x 190000h to 19ffffh c8000h to cffffh sa26 1 1 0 1 0 x x x 1a0000h to 1affffh d0000h to d7fffh sa27 1 1 0 1 1 x x x 1b0000h to 1bffffh d8000h to dffffh sa28 1 1 1 0 0 x x x 1c0000h to 1cffffh e0000h to e7fffh sa29 1 1 1 0 1 x x x 1d0000h to 1dffffh e8000h to effffh sa30 1 1 1 1 0 x x x 1e0000h to 1effffh f0000h to f7fffh sa31 1 1 1 1 1 0 x x 1f0000h to 1f7fffh f8000h to fbfffh sa32 1 1 1 1 1 1 0 0 1f8000h to 1f9fffh fc000h to fcfffh sa33 1 1 1 1 1 1 0 1 1fa000h to 1fbfffh fd000h to fdfffh sa34 1 1 1 1 1 1 1 x 1fc000h to 1fffffh fe000h to fefffh
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 18 sector address table (mbm29lv160b) sector address a 19 a 18 a 17 a 16 a 15 a 14 a 13 a 12 ( 8) address range ( 16) address range sa0 0 0 0 0 0 0 0 x 00000h to 03fffh 00000h to 01fffh sa1 0 0 0 0 0 0 1 0 04000h to 05fffh 02000h to 02fffh sa2 0 0 0 0 0 0 1 1 06000h to 07fffh 03000h to 03fffh sa3 0 0 0 0 0 1 0 x 08000h to 0ffffh 04000h to 07fffh sa4 0 0 0 0 1 x x x 10000h to 1ffffh 08000h to 0ffffh sa5 0 0 0 1 0 x x x 20000h to 2ffffh 10000h to 17fffh sa6 0 0 0 1 1 x x x 30000h to 3ffffh 18000h to 1ffffh sa7 0 0 1 0 0 x x x 40000h to 4ffffh 20000h to 27fffh sa8 0 0 1 0 1 x x x 50000h to 5ffffh 28000h to 2ffffh sa9 0 0 1 1 0 x x x 60000h to 6ffffh 30000h to 37fffh sa10 0 0 1 1 1 x x x 70000h to 7ffffh 38000h to 3ffffh sa11 0 1 0 0 0 x x x 80000h to 8ffffh 40000h to 47fffh sa12 0 1 0 0 1 x x x 90000h to 9ffffh 48000h to 4ffffh sa13 0 1 0 1 0 x x x a0000h to affffh 50000h to 57fffh sa14 0 1 0 1 1 x x x b0000h to bffffh 58000h to 5ffffh sa15 0 1 1 0 0 x x x c0000h to cffffh 60000h to 67fffh sa16 0 1 1 0 1 x x x d0000h to dffffh 68000h to 6ffffh sa17 0 1 1 1 0 x x x e0000h to effffh 70000h to 77fffh sa18 0 1 1 1 1 x x x f0000h to fffffh 78000h to 7ffffh sa19 1 0 0 0 0 x x x 100000h to 1fffffh 80000h to 87fffh sa20 1 0 0 0 1 x x x 110000h to 11ffffh 88000h to 8ffffh sa21 1 0 0 1 0 x x x 120000h to 12ffffh 90000h to 97fffh sa22 1 0 0 1 1 x x x 130000h to 13ffffh 98000h to 9ffffh sa23 1 0 1 0 0 x x x 140000h to 14ffffh a0000h to a7fffh sa24 1 0 1 0 1 x x x 150000h to 15ffffh a8000h to 8ffffh sa25 1 0 1 1 0 x x x 160000h to 16ffffh b0000h to b7fffh sa26 1 0 1 1 1 x x x 170000h to 17ffffh b8000h to bffffh sa27 1 1 0 0 0 x x x 180000h to 18ffffh c0000h to c7fffh sa28 1 1 0 0 1 x x x 190000h to 19ffffh c8000h to cffffh sa29 1 1 0 1 0 x x x 1a0000h to 1affffh d0000h to d7fffh sa30 1 1 0 1 1 x x x 1b0000h to 1bffffh d8000h to dffffh sa31 1 1 1 0 0 x x x 1c0000h to 1cffffh e0000h to e7fffh sa32 1 1 1 0 1 x x x 1d0000h to 1dffffh e8000h to effffh sa33 1 1 1 1 0 x x x 1e0000h to 1effffh f0000h to f7fffh sa34 1 1 1 1 1 x x x 1f0000h to 1fffffh f8000h to fffffh
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 19 description a 6 to a 0 dq 15 to dq 0 query-unique ascii string ?qry? 10h 11h 12h 0051h 0052h 0059h primary oem command set 02h: amd/fj standard type 13h 14h 0002h 0000h address for primary extended table 15h 16h 0040h 0000h alternate oem command set (00h = not applicable) 17h 18h 0000h 0000h address for alternate oem extended table 19h 1ah 0000h 0000h v cc min (write/erase) dq 7 to dq 4 : 1 v dq 3 to dq 0 : 100 mv 1bh 0027h v cc max (write/erase) dq 7 to dq 4 : 1 v dq 3 to dq 0 : 100 mv 1ch 0036h v pp min voltage 1dh 0000h v pp max voltage 1eh 0000h typical timeout per single byte/word write 2 n s 1fh 0004h typical timeout for min size buffer write 2 n s 20h 0000h typical timeout per individual sector erase 2 n ms 21h 000ah typical timeout for full chip erase 2 n ms 22h 0000h max timeout for byte/word write 2 n times typical 23h 0005h max timeout for buffer write 2 n times typical 24h 0000h max timeout per individual sector erase 2 n times typical 25h 0004h max timeout for full chip erase 2 n times typical 26h 0000h device size = 2 n byte 27h 0015h flash device interface description 02h : 8/ 16 28h 29h 0002h 0000h max number of bytes in multi-byte write = 2 n 2ah 2bh 0000h 0000h number of erase block regions within device 2ch 0004h common flash memory in terface code table description a 6 to a 0 dq 15 to dq 0 erase block region 1 information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z 256 bytes) 2dh 2eh 2fh 30h 0000h 0000h 0040h 0000h erase block region 2 information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z 256 bytes) 31h 32h 33h 34h 0001h 0000h 0020h 0000h erase block region 3 information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z 256 bytes) 35h 36h 37h 38h 0000h 0000h 0080h 0000h erase block region 4 information bit 15 to bit 0 : y = number of sectors bit 31 to bit 16 : z = size (z 256 bytes) 39h 3ah 3bh 3ch 001eh 0000h 0000h 0001h query-unique ascii string ?pri? 40h 41h 42h 0050h 0052h 0049h major version number, ascii 43h 0031h minor version number, ascii 44h 0030h address sensitive unlock 00h = required 45h 0000h erase suspend 02h = to read & write 46h 0002h sector protect 00h = not supported x = number of sectors in per group 47h 0001h sector temporary unprotect 01h = supported 48h 0001h sector protection algorithm 49h 0004h
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 20 functional description read mode the mbm29lv160t/b has two control functions which must be satisfied in order to obtain data at the outputs. ce is the power control and should be used for a device selection. oe is the output control and should be used to gate data to the output pins if a device is selected. address access time (t acc ) is equal to the delay from stable addresses to valid output data. the chip enable access time (t ce ) is the delay from stable addresses and stable ce to valid data at the output pins. the output enable access time is the de lay from the falling edge of oe to valid data at the output pins. (assuming the addresses have been stable for at least t acc - t oe time.) see ?(1) ac waveforms for read operations? in timing diagram for timing specifications. standby mode there are two ways to implement the standby mode on the mbm29lv160t/b devices. one is by using both the ce and reset pins; the other via the reset pin only. when using both pins, a cmos standby mode is achieved with ce and reset inputs both held at v cc 0.3 v. under this condition the current consumed is less than 5 a max. during embedded algorithm operation, v cc active current (i cc2 ) is required even ce = ?h?. the device can be read with standard access time (t ce ) from either of these standby modes. when using the reset pin only, a cmos standby mode is achieved with the reset input held at v ss 0.3 v (ce = ?h? or ?l?). under this condition the current consumed is less than 5 a max. once the reset pin is taken high, the device requires t rh of wake up time before outputs are valid for read access. in the standby mode, the outputs are in the high-impedance state, independent of the oe input. automatic sleep mode there is a function called automatic sleep mode to restrain power consumption during read-out of mbm29lv160t/b data. this mode can be used effectively with an application requesting low power consumption such as handy terminals. to activate this mode, mbm29lv160t/b automatically switch es itself to low power mode when addresses remain stable for 150 ns. it is not necessary to control ce , we , and oe in this mode. during such mode, the current consumed is typically 1 a (cmos level). standard address access timings provide new data when addresses are changed. while in sleep mode, output data is latched and always available to the system. output disable if the oe input is at a logic high level (v ih ), output from the device is disabled . this will cause t he output pins to be in a high-impedance state. autoselect the autoselect mode allows th e reading out of a binary code from the device and will identify its manufacturer and type. the intent is to allow programming equipment to automatically match the device to be programmed with its corresponding programming algorithm. the autoselect command may also be used to check the status of write-protected sectors. (see ?mbm29lv160t/b sector protection verify autoselect code table? and ?extended autoselect code table? in device bus operation.) this mode is functional over the entire temperature range of the device. to activate this mode, the programming equipment must force v id (11.5 v to 12.5 v) on address pin a 9 . two identifier bytes may then be sequenced from the devices outputs by toggling address a 0 from v il to v ih . all addresses are don?t cares except a 0 , a 1 , and a 6 (a -1 ). (see ?mbm29lv160t/b user bus operation tables (byte = v ih or byte = v il ) ? in device bus operation.) the manufacturer and device codes may also be read via the command register, for instances when the mbm29lv160t/b is erased or programmed in a system without access to high voltage on the a 9 pin. the command sequence is illust rated in ?mbm29lv160t/b standard command definitions table? in device bus operation.
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 21 byte 0 (a 0 = v il ) represents the manufacture?s code and byte 1 (a 0 = v ih ) represents the device identifier code. for the mbm29lv160t/b these two bytes are given in ?extended autoselect code table? (in device bus operation). all identifiers for manufactures and device will exhibit odd parity with dq 7 defined as the parity bit. in order to read the proper device codes when executing the autoselect, a 1 must be v il . (see ?mbm29lv160t/b user bus operation tables (byte = v ih and byte = v il )? in device bus operation.) for device indentification in word mode (byte = v ih ), dq 9 and dq 13 are equal to ?1? and dq 15 , dq 14 , dq 12 to dq 10 and dq 8 are equal to ?0?. if byte = v il (for byte mode), the device code is c4h (for top boot block) or 49h (for bottom boot block). if byte = v ih (for word mode), the device code is 22c4h (for top boot block) or 2249h (for bottom boot block). in order to determine which sectors are write protected, a 1 must be at v ih while running through the sector addresses; if the selected sector is protected, a lo gical ?1? will be output on dq 0 (dq 0 =1). write device erasure and programming are accomplished via the command register. the command register is written by bringing we to v il , while ce is at v il and oe is at v ih . addresses are latched on the falling edge of ce or we , whichever occurs later, while data is latched on the rising edge of ce or we pulse, whichever occurs first. standard microprocessor write timings are used. see ?(3) ac waveforms for alternate we controlled program operations? and ?(4) ac waveforms for alternate ce controlled program operations? and ?(5) ac waveforms for chip/sector erase operations? in timing diagram. refer to ac write characteristics and the erase/programming waveforms for specific timing parameters. sector protection the mbm29lv160t/b features hardware sector protection. this featur e will disable both program and erase operations in any number of sectors (0 through 34). the sector protection feature is enabled using programming equipment at the user?s site. the device is shipped with all sectors unprotected. to activate this mode, the programming equipment must force v id on address pin a 9 and control pin oe , ce = v il , a 0 = a 6 = v il , a 1 = v ih . the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) should be set to the sector to be protected. ?sector address tables (mbm29lv160t/b)? in flexible sector-erase architecture define the sector address for each of the thirty five (35) individual sectors. programming of the protection circuitry begins on the falling edge of the we pulse and is terminated with the rising edge of the same. sector addresses must be held constant during the we pulse. see ?(13) ac waveforms for sector protection timing diagram? in timing diagram and ?(5) sector protection algorithm? in flow chart for sector protection waveforms and algorithm. to verify programming of the protection circuitry, the programming equipment must force v id on address pin a 9 with ce and oe at v il and we at v ih . scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logi cal ?1? at device output dq 0 for a protected sector. otherwise the device will read 00h for an unprotec ted sector. in this mode, the lowe r order addresses, except for a 0 , a 1 , and a 6 are don?t cares. address locations with a 1 = v il are reserved for autoselect manufacturer and device codes. a -1 requires to v il in byte mode. it is also possible to determine if a sector is protected in the system by writing an autoselect command. performing a read operation at the address location xx02h, where the higher order addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) represents the sect or address will produce a logical ?1? at dq 0 for a protected sector. see ?mbm29lv160t/b sector protection verify autoselect code table? and ?extended autoselect code table? in device bus operation for autoselect codes. temporary sector unprotection this feature allows temporary unprotection of previous ly protected sectors of the mbm29lv160t/b devices in order to change data. the sector unprotecti on mode is activated by setting the reset pin to high voltage (12 v). during this mode, formerly protected sectors can be programmed or erased by selecting the sector addresses. once the 12 v is taken away from the reset pin, all the previously prot ected sectors will be protected again. (see ?(15) temporary sector unprotection timing diagram? in timing diagram and ?(6) temporary sector unprotection algorithm? in flow chart.)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 22 command definitions device operations are selected by writing specific address and data sequences into the command register. writing incorrect address and data valu es or writing them in an improper sequence will reset the device to the read mode. ?mbm29lv160t/b standard command definitions? in device bus operation defines the valid register command sequences. note that the erase su spend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. moreover both read/reset commands are functionally equivalent, resetting the device to the read mode. please note that commands are always written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. read/reset command in order to return from autoselect mode or exceeded timing limits (dq 5 = 1) to read mode, the read/reset operation is initiated by writing the read/reset command sequence into the command register. microprocessor read cycles retrieve array data from the memory. th e device remains enabled fo r reads until the command register contents are altered. the device will automatically power-up in the read/reset st ate. in this case, a command sequence is not required to read data. standard micr oprocessor read cycles will retrieve array data. this default va lue ensures that no spurious alteration of the memory contents occurs during the power transition. refer to the ac read characteristics and waveforms for specific timing parameters. (see ?(1) ac waveforms for read operations? in timing diagram.) autoselect command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manufactures and device codes must be accessible wh ile the device resides in the target system. prom programmers typically access the signature codes by raising a 9 to a high voltage. however, multiplexing high voltage onto the address lines is not generally desired system design practice. the device contains an autoselect command operation to supplement traditional prom programming methodology. the operation is initiated by writing the autoselect command sequence into the command register. following the last command write, a read cycle from address xx00h retrieves the manufacture code of 04h. a read cycle from address xx01h for 16 (xx02h for 8) retrieves the device code (mbm29lv160t = c4h and mbm29lv160b = 49h for 8 mode; mbm29lv160t = 22c4h and mbm29lv160b = 2249h for 16 mode). (see ?mbm29lv160t/b sector protection verify autoselect code table? and ?extended autoselect code table? in device bus operation.) all manufactures and device code s will exhibit odd parity with dq 7 defined as the parity bit. the sector state (pro tection or unprotection) will be indicated by address xx02h for 16 (xx04h for 8). scanning the sector addresses (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 , and a 12 ) while (a 6 , a 1 , a 0 ) = (0, 1, 0) will produce a logical ?1? at device output dq 0 for a protected sector. the programming verification should be perform margin mode verification on the protected sector. (see ?mbm29lv160t/b user bus operation tables (byte = v ih and byte = v il )? in device bus operation.) to terminate the operation, it is necessary to write the read/reset command sequence into the register and, also to write the autoselect command during the operation, by executing it after writing the read/reset command sequence. word/byte programming the device is programmed on a byte-by-byte (or word-by-word) basis. programming is a four bus cycle operation. there are two ?unlock? write cycles. these are followed by the program set-up command and data write cycles. addresses are latched on the falling edge of ce or we , whichever happens later and the data is latched on the rising edge of ce or we , whichever happens first. the rising edge of the last ce or we (whichever happens first) begins programming. upon executing the embedded program algorithm command sequence, the system is not required to provide further co ntrols or timings. the device will auto matically provide a dequate internally generated program pulses and verify the programmed cell margin. (see ?(3) ac waveforms for alternate we controlled program operations? and ?(4) ac waveforms for alternate ce controlled program operations? in timing diagram.)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 23 the automatic programming operation is completed when the data on dq 7 is equivalent to data written to this bit at which time the device return to the read mode and addresses are no longer latched. (see ?hardware sequence flags table?.) therefore, the device requires that a valid address be supplied by the system at this time. hence, data polling must be performed at the memory location which is being programmed. any commands written to the chip during this period will be ignored. if hardware reset occures during the programming operation, it is impossible to guarantee whether the data being written is correct or not. programming is allowed in any sequence and across sector boundaries. beware that a data ?0? cannot be programmed back to a ?1?. attempting to do so may either hang up the device or result in an apparent success according to the data polling algorithm bu t a read from read /reset mode will show that the data is still ?0?. only erase operations can convert ?0?s to ?1?s. ?(1) embedded program tm algorithm? in flow chart illustrates the embedded program tm algorithm using typical command strings and bus operations. chip erase chip erase is a six-bus cycle operation. there are two ?unlock? write cycles. these are followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the chip erase command. chip erase does not require the user to program the device prior to erase. upon executing the embedded erase algorithm command sequenc e the device will automatically program and verify the entire memory for an all zero data pattern prior to electrical erase. (preprogram function.) the system is not required to provide any controls or timings during these operations. the automatic erase begins on the rising edge of the last we pulse in the command sequence and terminates when the data on dq 7 is ?1? (see write operation status section.) at which time the device returns to read mode. (see ?(5) ac waveforms for chip/sector erase operations? in timing diagram.) ?(2) embedded erase tm algorithm? in flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. sector erase sector erase is a six-bus cycle operation. there are two ?unlock? write cycles, followed by writing the ?set-up? command. two more ?unlock? write cycles are then followed by the sector erase command. the sector address (any address location within t he desired sector) is latche d on the falling edge of we , while the command (data = 30h) is latched on the rising edge of we . after a time-out of 50 s from the rising edge of the last sector erase command, the sector erase operation will begin. multiple sectors may be erased concurrently by writing six-bus cycle operations on ?mbm29lv160t/b standard command definitions? in device bus operation. this sequence is followed with writes of the sector erase command to addresses in other sectors desired to be concurrently erased. the time between writes must be less than 50 s otherwise that comma nd will not be accepted and erasure will start. it is recommended that processor interrupts be disabled during this time to guarantee this condition. the interrupts can be re-enabled after the last sector erase command is written. a time-out of 50 s from the rising edge of the last we will initiate the execution of the sector erase comm and(s). if another fa lling edge of the we occurs within the 50 s time- out window the timer is reset. monitor dq 3 to determine if the sector erase ti mer window is still open. (see section dq 3 , sector erase timer.) any command other than sector erase or erase suspend during this time-out period will reset the device to the read mode, ignoring the previous command string. resetting the device once excution has begun will corrupt the data in the sector. in that case, restart the er ase on those sectors and allow them to complete. (refer to the write operation status section for sector erase timer operation.) loading the sector erase buffer may be done in any sequence and with any number of sectors (0 to 34). sector erase does not require the user to program the device prior to erase. the device automatically programs all memory locations in the sector(s) to be erased prio r to electrical erase (preprogram function). when erasing a sector or sectors the remaining unselected sectors are not affected. the system is not required to provide any controls or timings during these operations. (see ?(5) ac waveforms for chip/sector erase operations? in timing diagram.)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 24 the automatic sector erase begins after the 50 s time out from the rising edge of the we pulse for the last sector erase command pulse and terminates when the data on dq 7 is ?1? (see write operation status section) at which time the device returns to the read mode. data polling must be performed at an address within any of the sectors being erased. multiple sector erase time; [sector program time (preprogramming) + sector erase time] number of sector erase. ?(2) embedded erase tm algorithm? in flow chart illustrates the embedded erase tm algorithm using typical command strings and bus operations. erase suspend/resume the erase suspend command allows the user to interrupt a sector erase operation and then perform data reads from or program to a sector not being erased. this command is applicable only during the sector erase operation which includes t he time-out period for sector erase. the erase suspend command will be ignored if written during the chip erase operation or embedded program algorithm. writting the erase suspend command during the sector erase time-out results in immediate termination of the time-out period and suspension of the erase operation. writing the erase resume command resumes the erase operation. the addresses are ?don?t cares? when writing the erase suspend or erase resume commands. when the erase suspend command is writ ten during the se ctor erase operation, the device will take a maximum of 20 s to suspend the erase operation. when the devices have entered the erase-suspended mode, the ry/ by output pin and the dq 7 bit will be at logic ?1?, and dq 6 will stop toggling. the user must use the address of the erasing sector for reading dq 6 and dq 7 to determine if the erase operation has been suspended. further writes of the erase suspend command are ignored. when the erase operation has been suspended, the device defaults to the erase-suspend-read mode. reading data in this mode is the same as reading from the standard read mode except that the data must be read from sectors that have not been erase-suspended. successively reading from the erase-suspended sector while the device is in the erase-suspend-read mode will cause dq 2 to toggle. (see the section on dq 2 .) after entering the erase-suspend-read mode, the user can program the device by writing the appropriate command sequence for program. this program mode is known as the erase-suspend-program mode. again, programming in this mode is the same as programming in the regular program mode except that the data must be programmed to sectors that are not erase-suspended. successively reading from the erase-suspended sector while the devices are in the eras e-suspend-program mode will cause dq 2 to toggle. the end of the erase- suspended program operation is detected by the ry/by output pin, data polling of dq 7 , or the toggle bit (dq 6 ) which is the same as the regular program operation. note that dq 7 must be read from the program address while dq 6 can be read from any address. to resume the operation of sector erase, the resume command (30h) should be written. any further writes of the resume command at this point will be ignored. another erase suspend comman d can be written after the chip has resumed erasing. extended command (1) fast mode mbm29lv160t/b has fast mode function. this mode dispenses with the initial two unlock cycles required in the standard program command sequence writing fast mode command into the command register. in this mode, the required bus cycle for programming is two cycles instead of four bus cycles in standard program command. the read operation is also executed after exiting this mode. during the fast mode, do not write any command other than the fast program/fast mode reset command. to exit this mode, it is necessary to write fast mode reset command into the command register. (refer to ?(7) embedded programming algorithm for fast mode? in flow chart.) the v cc active current is required even ce = v ih during fast mode. (2) fast programming during fast mode, the programming can be executed with two bus cycles operation. the embedded program algorithm is executed by writing program set-up command (a0h) and data write cycles (pa/pd). (refer to ?(7) embedded programming algorithm for fast mode? in flow chart.)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 25 (3) cfi (common flash memory interface) the cfi (common flash memory interface) specific ation outlines device and host system software interrogation handshake which allows specific vendor-s pecified software algorithms to be used for entire families of devices. this allows device-independen t, jedec id-independent, and forward-and backward- compatible software support for the specified flash device families. re fer to cfi specification in detail. the operation is initiated by writ ing the query command (98h) into the command register. following the command write, a read cycle from specific address retriv es device information. please note that output data of upper byte (dq 15 to dq 8 ) is ?0? in word mode (16 bit) read. refer to ?common flash memory interface code table? in flexible sector-erase architecture. to term inate operation, it is necessary to write the read/reset command sequence into the register. (4) extended sector protect in addition to normal sector protection, the mbm29lv160t/b has extended sector protection as extended function. this function enable to protect sector by forcing v id on reset pin and write a commnad sequence. unlike conventional procedure, it is not necessary to force v id and control timing for control pins. the only reset pin requires v id for sector protection in this mode. the extended sector protect requires v id on reset pin. with this condition, the operation is initiated by writing the set-up command (60h) into the command register. then, the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set to the sector to be protected (recommend to set v il for the other addresses pins), and write extended sector protect command (60h). a sector is typically protected in 150 s. to verify programming of the protection circuitry, the sector addresses pins (a 19 , a 18 , a 17 , a 16 , a 15 , a 14 , a 13 and a 12 ) and (a 6 , a 1 , a 0 ) = (0, 1, 0) should be set and write a command (40h). following the command write, a logical ?1? at device output dq 0 will produce for protected se ctor in the read operat ion. if the output data is logical ?0?, please repeat to write extended sector protect command (60h) again. to terminate the operation, it is necessary to set reset pin to v ih . write operation status *1 : performing successive read oper ations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic ?1? at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. notes : ? dq 0 and dq 1 are reserve pins for future use. ? dq 4 is fujitsu internal use only. hardware sequence flags table status dq 7 dq 6 dq 5 dq 3 dq 2 in progress embedded program algorithm dq 7 toggle 0 0 1 embedded/erase algorithm 0 toggle 0 1 toggle erase suspend mode erase suspend read (erase suspended sector) 1100toggle erase suspend read (non-erase suspended sector) data data data data data erase suspend program (non-erase suspended sector) dq 7 toggle* 1 00 1* 2 exceeded time limits embedded program algorithm dq 7 toggle 1 0 1 embedded/erase algorithm 0 toggle 1 1 n/a erase suspend program (non-erase suspended sector) dq 7 toggle 1 0 n/a
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 26 dq 7 data polling the mbm29lv160t/b device features data polling as a method to indicate to the host that the embedded algorithms are in progress or completed. during the embedded program algorithm, an attempt to read the devices will produce the complement of the data last written to dq 7 . upon completion of the embedded program algorithm, an attempt to read the device w ill produce the true data last written to dq 7 . during the embedded erase algorithm, an atte mpt to read the device will produce a ?0? at the dq 7 output. upon completion of the embedded erase algorithm an attempt to re ad the device will produ ce a ?1? at the dq 7 output. the flowchart for data polling (dq 7 ) is shown in ?(3) data polling algorithm? in flow chart. for chip erase and sector erase, data polling is valid after the rising edge of the sixth we pulse in the six-write pulse sequence. data polling must be performed at a sector addre ss within any of the sectors being erased and not at a protected sector. otherwise, the status may not be valid. once the embedded algorithm operation is close to being completed, the mbm29lv160t/b data pins (dq 7 ) may change asynchronously while the output enable (oe ) is asserted low. this means that the device is driving status information on dq 7 at one instant of time and then that byte?s valid data at the next instant of time. depending on when the system samples the dq 7 output, it may read the status or valid data. even if the device has completed the embedded program algorithm operation and dq 7 has a valid data, the data outputs on dq 6 to dq 0 may be still invalid. the valid data on dq 7 to dq 0 will be read on successive read attempts. the data polling feature is only active during the embedd ed programming algorithm, embedded erase algorithm or sector erase time-out. see ?(6) ac waveforms for data polling during embedded algorithm operations? in timing diagram for the data polling timing specifications and diagrams. dq 6 toggle bit i the mbm29lv160t/b also feature the ?toggle bit i? as a method to indicate to the host system that the embedded algorithms are in progress or completed. during an embedded program or erase algorith m cycle, successive attempts to read (oe toggling) data from the device will result in dq 6 toggling between one and zero. once the embedded program or erase algorithm cycle is completed, dq 6 will stop toggling and valid data can be re ad on the next successive attempts. during programming, the toggle bit i is valid after the rising edge of the fourth we pulse in the four write pulse sequence. for chip erase and sector erase, the toggle bit i is valid after the rising edge of the sixth we pulse in the six- write pulse sequence. the toggle bit i is active during the sector time out. in programming, if the sector being written to is protected, the toggle bit will toggle for about 2 s and then stop toggling without the data having changed. in erase, the device will erase a ll the selected sectors except for the ones that are protected. if all select ed sectors are protected, the chip will toggle the toggle bit i for about 200 s and then drop back into read mode, having changed none of the data. either ce or oe toggling will cause the dq 6 to toggle. in addi tion, an erase suspen d/resume command will cause the dq 6 to toggle. see ?(7) ac waveforms for toggle bit i during embedded algorithm operations? in timing diagram and ?(4) toggle bit algorithm? in flow chart for the toggle bit i timing specifications and diagrams. dq 5 exceeded timing limits dq 5 will indicate if the program or erase time has ex ceeded the specified limits (internal pulse count). under these conditions dq 5 will produce a ?1?. this is a failure conditio n which indicates that the program or erase cycle was not successfully completed. data polling is the only operating f unction of the device under this condition. the ce circuit will partially power down the device under these conditions. the oe and we pins will control the output disable functions as described in ?mbm29lv160t/b user bus operation tables (byte = v ih and byte = v il )? (in device bus operation).
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 27 the dq 5 failure condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the embedded algorithm operation. hence, the system never reads a valid data on dq 7 and dq 6 never stops toggling. once the device has exceeded timing limits, the dq 5 bit will indicate a ?1.? please note that this is not a device failure conditi on since the device was incorrectly used. if this occurs, reset the device with command sequence. dq 3 sector erase timer after the completion of t he initial sector erase comm and sequence the sector er ase time-out will begin. dq 3 will remain low until the time -out is complete. data polling and toggle bit i are valid after the initia l sector erase command sequence. if data polling or the toggle bit i indicates the device has been written with a valid erase command, dq 3 may be used to determine if the sector erase timer window is still open. if dq 3 is high (?1?) the internally controlled erase cycle has begun; atte mpts to write subsequent co mmands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit i. if dq 3 is low (?0?), the device will accept additional sector erase commands. to insure the command has been accepted, the system software should check the status of dq 3 prior to and following each subsequent sector erase command. if dq 3 is high on the second status check, the command may not have been accepted. see ?hardware sequence flags table?. dq 2 toggle bit ii this toggle bit ii, along with dq 6 , can be used to determine whether the device is in the embedded erase algorithm or in erase suspend. successive reads from the erasing sector will cause dq 2 to toggle during the embedded erase algorithm. if the device is in the erase- suspended-read mode, successive reads fr om the erase-suspended sector will cause dq 2 to toggle. when the device is in the erase-suspended-program mode, successive reads from the byte address of the non-erase suspended sector will indi cate a logic ?1? at dq 2 . dq 6 is different from dq 2 in that dq 6 toggles only when the standard program or erase, or erase suspend program operation is in progress. for example, dq 2 and dq 6 can be used together to determine if the erase-suspend-read mode is in progress. (dq 2 toggles while dq 6 does not.) see also ?toggle bit status table? and ?(16) dq 2 vs. dq 6 ? in timing diagram. furthermore, dq 2 can also be used to determine which sector is being erased. when the device is in the erase mode, dq 2 toggles if this bit is read from an erasing sector. *1 : performing successive read oper ations from any address will cause dq 6 to toggle. *2 : reading the byte address being programmed while in the erase-suspend program mode will indicate logic ?1? at the dq 2 bit. however, successive reads from the erase-suspended sector will cause dq 2 to toggle. toggle bit status table mode dq 7 dq 6 dq 2 program dq 7 toggle 1 erase 0 toggle toggle erase suspend read (erase suspended sector)* 1 1 1 toggle erase-suspend program dq 7 toggle* 1 1 * 2
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 28 ry/by ready/busy pin the mbm29lv160t/b provides a ry/by open-drain output pin as a way to indicate to the host system that the embedded algorithms are either in progress or has been completed. if the output is low, the device is busy with either a program or erase operation. if the output is high, the device is ready to accept any read/write or erase operation. when the ry/by pin is low, the devices will not accept any additional program or erase commands with the exception of the erase suspend command. if the mbm29lv160t/b is placed in an erase suspend mode, the ry/by output will be high, by means of connec ting with a pull-up resister to v cc . during programming, the ry/by pin is driven low after the rising edge of the fourth we pulse. during an erase operation, the ry/by pin is driven low after the rising edge of the sixth we pulse. the ry/by pin will indicate a busy condition during the reset pulse. see ?(8) ry/by timing diagram during program/erase operations? and ?(9) reset , ry/by timing diagram? in timing diagram for a detailed timing diagram. the ry/by pin is pulled high in standby mode. since this is an open-drain output, the pu ll-up resistor needs to be connected to v cc ; multiples of devices may be connected to the host system via more than one ry/by pin in parallel. reset hardware reset pin the mbm29lv160t/b device may be reset by driving the reset pin to v il . the reset pin has a pulse requirement and has to be kept low (v il ) for at least 500 ns in order to properly reset the internal state machine. any operation in the proces s of being executed will be terminated a nd the internal state machine will be reset to the read mode t ready after the reset pin is driven low. furthermore, once the reset pin goes high, the device requires an additional t rh before it allows read access. when the reset pin is low, the device will be in the standby mode for the duration of t he pulse and all the data output pins will be tri-stated. if a hardware reset occurs during a program or erase operat ion, the data at that particular location will be corrupted. please note that the ry/by output signal should be ignored during the reset pulse. refer to ?(9) reset , ry/by timing diagram? in timing diagram for the timing diagram. refer to temporary sector unprotection for additional functionality. if hardware reset occurs during embedded erase algorith m, there is a possibility t hat the erasing sector(s) will need to be erased again before they can be programmed. word/byte configuration the byte pin selects the byte (8-bit) mode or word (16-bit) mode for the mbm29lv160t/b device. when this pin is driven high, the device operates in the word (16-bit) mode. the data is read and programmed at dq 15 to dq 0 . when this pin is driven low, the device operates in byte (8-bit) mode. under this mode, dq 15 /a -1 pin becomes the lowest address bit and dq 14 to dq 8 bits are tri-stated. however, the command bus cycle is always an 8-bit operation and hence commands are written at dq 7 to dq 0 and dq 15 to dq 8 bits are ignored. refer to ?(10) timing diagram for word mode configuration? and ?(11) timing diagram for byte mode configuration? in timing diagram for the timing diagrams. data protection the mbm29lv160t/b is designed to offer protection ag ainst accidental erasure or programming caused by spurious system level signals that may exist during power transitions. during power up the device automatically resets the internal state machine to the read mode. also, with its control register architecture, alteration of the memory contents only occurs after successful comp letion of specific multi-bus cycle command sequence. the device also incorporates several features to prevent inadvertent write cycles resulting form v cc power-up and power-down transitions or system noise. low v cc write inhibit to avoid initiation of a write cycle during v cc power-up and power-down, a write cycle is locked out for v cc less than 2.3 v (typically 2.4 v). if v cc < v lko , the command register is disabled and all internal program/erase circuits are disabled. under this condition, the device will reset to the read mode. subsequent writes will be ignored until
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 29 the v cc level is greater than v lko . it is the users responsibility to ensure th at the control pins are logically correct to prevent unintentional writes when v cc is above 2.3 v. if the embedded erase algorithm is in terrupted, there is possibility that the erasing sector(s) will need to be erased again prior to programming. write pulse ?glitch? protection noise pulses of less than 3 ns (typical) on oe , ce , or we will not change th e command registers. logical inhibit writing is inhibited by holding any one of oe = v il , ce = v ih , or we = v ih . to initiate a write, ce and we must be a logical zero while oe is a logical one. power-up write inhibit power-up of the devices with we = ce = v il and oe = v ih will not accept commands on the rising edge of we . the internal state machine is automatically reset to read mode on power-up. sector protection device user is able to protect each sector individually to store and protect data. protection circuit voids both program and erase commands that are addressed to protect sectors. any command to program or erase addressed to protected sector are ignored (see ?sector protection? in functional description).
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 30 absolute maximum ratings *1: voltage is defined on the basis of v ss = gnd = 0 v. *2: minimum dc voltage on input or l/o pins is ?0.5 v. during voltage transitions, input or i/o pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. maximum dc voltage on input or l/o pins is v cc +0.5 v. during voltage transitions, input or i/o pins may overshoot to v cc +2.0 v for periods of up to 20 ns. *3: minimum dc input voltage on a 9 , oe , and reset pins is ?0.5 v. during voltage transitions, a 9 , oe , and reset pins may undershoot v ss to ?2.0 v for periods of up to 20 ns. voltage difference between input and supply voltage (v in ? v cc ) does not exceed + 9.0 v. maximum dc input voltage on a 9 , oe , and reset pins are +13.0 v which may overshoot to + 14.0 v for periods of up to 20 ns. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. recommended operating conditions * : voltage is defined on the basis of v ss = gnd = 0 v. note : operating ranges define those limits between which the functionality of the devices are guaranteed. warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device?s electric al characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may advers ely affect reliability and coul d result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol rating unit min max storage temperature tstg ? 55 + 125 c ambient temperature with power applied t a ? 40 + 85 c voltage with respect to ground all pins except a 9 , oe , reset * 1, * 2 v in , v out ? 0.5 v cc + 0.5 v a 9 , oe and reset * 1, * 3 v in ? 2.0 + 13.0 v power supply voltage* 1 v cc ? 0.5 + 5.5 v parameter symbol part number value unit min max ambient temperature t a mbm29lv160t/b-80 ? 20 + 70 c mbm29lv160t/b-90/-12 ? 40 + 85 c power supply voltage* v cc mbm29lv160t/b-80 + 3.0 + 3.6 v mbm29lv160t/b-90/-12 + 2.7
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 31 maximum overshoot/ maximum undershoot maximum undershoot waveform +0.6 v ?0.5 v 20 ns ?2.0 v 20 ns 20 ns maximum overshoot waveform 1 +2.0 v v cc +0.5 v 20 ns v cc +2.0 v 20 ns 20 ns maximum overshoot waveform 2 v cc +0.5 v +13.0 v 20 ns +14.0 v 20 ns 20 ns note : this waveform is applied for a 9 , oe , and reset .
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 32 dc characteristics *1 : the l cc current listed includes both the dc operating current and the frequency dependent component. *2 : l cc active while embedded erase or embedded program is in progress. *3 : automatic sleep mode enables the low power mode when address remain stable for 150 ns. *4 : the timing is only for sector protection operation and autoselect mode. *5 : (v id ? v cc ) do not exceed 9 v. parameter symbol test conditions min max unit input leakage current i li v in = v ss to v cc , v cc = v cc max ?1.0 +1.0 a output leakage current i lo v out = v ss to v cc , v cc = v cc max ?1.0 +1.0 a a 9 , oe , reset inputs leakage current i lit v cc = v cc max, a 9 , oe , reset = 12.5 v ?35a v cc active current * 1 i cc1 ce = v il , oe = v ih , f = 10 mhz byte ? 30 ma word 35 ce = v il , oe = v ih , f = 5 mhz byte ? 15 ma word 17 v cc active current * 2 i cc2 ce = v il , oe = v ih ?35ma v cc current (standby) i cc3 v cc = v cc max, ce = v cc 0.3 v, reset = v cc 0.3 v ?5a v cc current (standby, reset )i cc4 v cc = v cc max, reset = v ss 0.3 v ?5a v cc current (automatic sleep mode) * 3 i cc5 v cc = v cc max, ce = v ss 0.3 v, reset = v cc 0.3 v, v in = v cc 0.3 v or v ss 0.3 v ?5a input low voltage v il ??0.50.6v input high voltage v ih ?2.0v cc + 0.3 v voltage for autoselect,sector protection, and temporary sector unprotection (a 9 , oe , reset ) * 4, * 5 v id ?11.512.5v output low voltage v ol i ol = 4.0 ma, v cc = v cc min ? 0.45 v output high voltage v oh1 i oh = ?2.0 ma, v cc = v cc min 2.4 ? v v oh2 i oh = ?100 a v cc ? 0.4 ? v low v cc lock-out voltage v lko ?2.32.5v
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 33 ac characteristics read only operations characteristics * : test conditions: output load: 1 ttl gate and 30 pf (mbm29lv160t/b-80/-90) 1 ttl gate and 100 pf (mbm29lv160t/b-12) input rise and fall times: 5 ns input pulse levels: 0.0 v or 3.0 v timing measurement reference level input: 1.5 v output: 1.5 v parameter symbol test setup -80* -90* -12* unit jedec standard min max min max min max read cycle time t avav t rc ?80 ? 90 ? 120 ? ns address to output delay t avqv t acc ce = v il oe = v il ? 80 ? 90 ? 120 ns chip enable to output delay t elqv t ce oe = v il ? 80 ? 90 ? 120 ns output enable to output delay t glqv t oe ? ? 30 ? 35 ? 50 ns chip enable to output high-z t ehqz t df ? ? 25 ? 30 ? 30 ns output enable to output high-z t ghqz t df ? ? 25 ? 30 ? 30 ns output hold time from address, ce or oe , whichever occurs first t axqx t oh ?0 ? 0 ? 0 ? ns reset pin low to read mode ? t ready ? ? 20 ? 20 ? 20 s ce to b yte switching low or high ? t elfl t elfh ? ? 5 ? 5 ? 5ns test conditions c l 3.3 v diode = 1n3064 or equivalent 2.7 k ? device under test diode = 1n3064 or equivalent 6.2 k ? notes: c l = 30 pf including jig capac itance (mbm29lv160t/b-80/-90) c l = 100 pf including jig c apacitance (mbm29lv160t/b-12)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 34 write (erase/program) operations *1 : this does not include the preprogramming time. *2 : this timing is for sector protection operation. parameter symbol -80 -90 -12 unit jedec standard min typ max min typ max min typ max write cycle time t avav t wc 80 ?? 90 ?? 120 ?? ns address setup time t avwl t as 0 ?? 0 ?? 0 ?? ns address hold time t wlax t ah 45 ?? 45 ?? 50 ?? ns data setup time t dvwh t ds 35 ?? 45 ?? 50 ?? ns data hold time t whdx t dh 0 ?? 0 ?? 0 ?? ns output enable setup time ? t oes 0 ?? 0 ?? 0 ?? ns output enable hold time read ?t oeh 0 ?? 0 ?? 0 ?? ns toggle and data polling 10 ?? 10 ?? 10 ?? ns read recover time before write t ghwl t ghwl 0 ?? 0 ?? 0 ?? ns read recover time before write (oe high to ce low) t ghel t ghel 0 ?? 0 ?? 0 ?? ns ce setup time t elwl t cs 0 ?? 0 ?? 0 ?? ns we setup time t wlel t ws 0 ?? 0 ?? 0 ?? ns ce hold time t wheh t ch 0 ?? 0 ?? 0 ?? ns we hold time t ehwh t wh 0 ?? 0 ?? 0 ?? ns write pulse width t wlwh t wp 35 ?? 45 ?? 50 ?? ns ce pulse width t eleh t cp 35 ?? 45 ?? 50 ?? ns write pulse width high t whwl t wph 25 ?? 25 ?? 30 ?? ns ce pulse width high t ehel t cph 25 ?? 25 ?? 30 ?? ns programming operation byte t whwh1 t whwh1 ? 8 ?? 8 ?? 8 ? s word ? 16 ?? 16 ?? 16 ? sector erase operation * 1 t whwh2 t whwh2 ? 1 ?? 1 ?? 1 ? s delay time from embedded output enable ?t eoe ?? 80 ?? 90 ?? 120 ns v cc setup time ? t vcs 50 ?? 50 ?? 50 ?? s voltage transition time * 2 ?t vlht 4 ?? 4 ?? 4 ?? s write pulse width * 2 ?t wpp 100 ?? 100 ?? 100 ?? s oe setup time to we active * 2 ?t oesp 4 ?? 4 ?? 4 ?? s ce setup time to we active * 2 ?t csp 4 ?? 4 ?? 4 ?? s recover time from ry/by ?t rb 0 ?? 0 ?? 0 ?? ns reset hold time before read ?t rh 200 ?? 200 ?? 200 ?? ns program/erase valid to ry/by delay ?t busy ?? 90 ?? 90 ?? 90 ns byte switching low to output high-z ?t flqz ?? 25 ?? 30 ?? 30 ns byte switching high to output active ?t fhqv ?? 80 ?? 90 ?? 120 ns rise time to v id * 2 ?t vidr 500 ?? 500 ?? 500 ?? ns reset pulse width ? t rp 500 ?? 500 ?? 500 ?? ns
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 35 erase and programm ing performance tsop (1) pin capacitance (f = 1.0 mhz, t a = + 25 c) note : dq 15 /a- 1 pin capacitance is stipulated by output capacitance. csop pin capacitance (f = 1.0 mhz, t a = + 25 c) note : dq 15 /a- 1 pin capacitance is stipulated by output capacitance. fbga pin capacitance (f = 1.0 mhz, t a = + 25 c) note : dq 15 /a- 1 pin capacitance is stipulated by output capacitance. parameter limits unit comments min typ max sector erase time ? 1 10 s excludes programming time prior to erasure byte programming time ? 8 360 s excludes system-level overhead word programming time ? 16 300 chip programming time ? 16.8 50 s excludes system-level overhead erase/program cycle 100,000 ? ? cycle ? parameter symbol test setup typ max unit input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 10 13 pf parameter symbol test setup typ max unit input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 10 13 pf parameter symbol test setup typ max unit input capacitance c in v in = 0 7.5 9.5 pf output capacitance c out v out = 0 8 10 pf control pin capacitance c in2 v in = 0 10 13 pf
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 36 timing diagram key to switching waveforms (1) ac waveforms for read operations waveform inputs outputs must be steady may change from h to l may change from l to h ?h? or ?l?: any change permitted does not apply will be steady will be change from h to l will be change from l to h changing, state unknown center line is high- impedance ?off? state we oe ce t df t ce t oe outputs address address stable high-z output valid high-z t oeh t acc t rc t oh
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 37 (2) ac waveforms for hardware reset/read operations (3) ac waveforms for alternate we controlled program operations reset t acc t oh outputs t rc address address stable high-z output valid t rh notes : ? pa is address of the memory location to be programmed. ? pd is data to be programmed at word address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates last two bus cycles out of four bus cycle sequence. ? these waveforms are for the 16 mode. (the addresses differ from 8 mode.) t ch t wp t whwh1 t wc t ah ce oe t rc address data t as t oe t wph t ghwl t dh dq 7 pd a0h d out we 555h pa pa t oh data polling 3rd bus cycle t cs t ce t ds d out t df
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 38 (4) ac waveforms for alternate ce controlled program operations notes : ? pa is address of the memory location to be programmed. ? pd is data to be programmed at word address. ? dq 7 is the output of the complement of the data written to the device. ? d out is the output of the data written to the device. ? figure indicates last two bus cycles out of four bus cycle sequence. ? these waveforms are for the 16 mode. (the addresses differ from 8 mode.) t cp t ds t whwh1 t wc t ah we oe address data t as t cph t dh dq 7 a0h d out ce 555h pa pa data polling 3rd bus cycle t ws t wh t ghel pd
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 39 (5) ac waveforms for chip/sector erase operations * : sa is the sector address for sector erase. addresses = 555h (word), aaaah (byte) for chip erase. note: these waveforms are for the 16 mode. (the addresses differ from 8 mode.) v cc ce oe address data we 555h 2aah 555h 555h 2aah sa* t ds t ch t as t ah t cs t wph t dh t ghwl t vcs t wc t wp aah 55h 80h aah 55h 10h/ 10h for chip erase 30h
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 40 (6) ac waveforms for data polling during embedded algorithm operations (7) ac waveforms for toggle bit i during embedded algorithm operations *:dq 7 = valid data (the device has completed the embedded operation.) t oeh t oe t whwh1 or 2 ce oe we data t df t ch t ce dq 7 = valid data dq 7 * data dq 6 to dq 0 = output flag (t eoe ) dq 6 to dq 0 valid data high-z high-z dq 7 dq 6 to dq 0 t busy ry/by * * : dq 6 = stops toggling. (the device has completed the embedded operation.) ce we oe data dq 6 = toggle dq 6 = stop toggling dq 7 to dq 0 data valid t oe dq 6 = toggle t oeh t oes t dh dq 6 t busy ry/by
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 41 (8) ry/by timing diagram during program/erase operations (9) reset , ry/by timing diagram (10) timing diagram for word mode configuration rising edge of the last we signal ce ry/by we t busy entire programming or erase operations t rp reset t ready ry/by we t rb ce byte dq 14 to dq 0 dq 15 /a -1 dq 15 t fhqv t elfh a -1 t ce data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 )
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 42 (11) timing diagram for byte mode configuration (12) byte timing diagram for write operations ce byte dq 14 to dq 0 dq 15 /a -1 t flqz t elfl a -1 dq 15 a -1 t acc data output (dq 7 to dq 0 ) data output (dq 14 to dq 0 ) ce falling edge of the last we signal we t ah t as input valid byte
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 43 (13) ac waveforms for sector protection timing diagram spax = sector addres s for initial sector spay = sector address for next sector note : a -1 is v il on byte mode. t vlht spax spay a 0 a 6 a 9 v id v ih oe v id v ih t vlht we ce 01h data a 1 a 19 , a 18 , a 17 t vlht a 16 , a 15 , a 14 a 13 , a 12 t wpp t vlht t oesp t csp t oe v cc t vcs
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 44 (14) extended sector protection timing diagram v cc a 0 a 1 a 6 oe we ce t oe time out data spax 01h reset t vcs t vidr spax spay address t vlht 60h 60h 40h 60h t wc t wc t wp spax : sector address to be protected spay : next sector address to be protected time-out : time-out window = 150 s (min)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 45 (15) temporary sector unprotection timing diagram (16) dq 2 vs. dq 6 v ih reset v cc ce we ry/by t vlht program or erase command sequence t vlht t vcs t vidr v id t vlht unprotection period * : dq 2 is read from the erase-suspended sector. dq 2 * dq 6 we erase erase suspend enter embedded erasing erase suspend read enter erase suspend program erase suspend program erase suspend read erase resume erase erase complete toggle dq 2 and dq 6 with oe or ce
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 46 flow chart (1) embedded program tm algorithm no yes 555h/aah 2aah/55h 555h/a0h no yes start write program command sequence (see below) data polling verify data ? last address ? programming completed program command sequence (address/command) : program address/program data increment address embedded program algorithm in progress embedded algorithm notes : ? the sequence is applied for 16 mode. ? the addresses differ from 8 mode.
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 47 (2) embedded erase tm algorithm 555h/aah 2aah/55h 555h/aah 555h/80h 555h/10h 2aah/55h 555h/aah 2aah/55h 555h/aah 555h/80h 2aah/55h no yes start write erase command sequence (see below) data polling data = ffh ? erasure completed embedded erase algorithm in progress chip erase command sequence (addresss/command) : individual sector/multiple sector erase command sequence (address/command) : sector address /30h additional sector erase commands are optional. sector address /30h sector address /30h embedded algorithm note : the sequence is applied for 16 mode. the addresses differ from 8 mode.
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 48 (3) data polling algorithm * : dq 7 is rechecked even if dq 5 = ?1? because dq 7 may change simultaneously with dq 5 . va =address for programming =any of the sector addresses within the sector being erased during sector erase or multiple sector erases operation. =any of the sector addresses within the sector not being protected during chip erases operation. fail dq 7 = data? no no dq 7 = data? dq 5 = 1? pass yes yes no start read byte (dq 7 to dq 0 ) addr. = va read byte (dq 7 to dq 0 ) addr. = va yes *
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 49 (4) toggle bit algorithm no dq 6 = toggle ? dq 5 = 1 ? yes no yes dq 6 = toggle ? yes no program/erase operation not complete. write reset command program/erase operation complete start read (dq 7 to dq 0 ) addr. = ?h? or ?l? read (dq 7 to dq 0 ) addr. = ?h? or ?l? *1 *1, *2 read (dq 7 to dq 0 ) addr. = ?h? or ?l? *1, *2 read (dq 7 to dq 0 ) addr. = ?h? or ?l? *1 *1 : read toggle bit twice to determine whether it is toggling. *2 : recheck toggle bit because it may stop toggling as dq 5 changes to ?1?.
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 50 (5) sector protection algorithm * : a -1 is v il on byte mode. setup sector addr. activate we pulse we = v ih , ce = oe = v il (a 9 should remain v id ) yes no no plscnt = 1 time out 100 s read from sector increment plscnt no yes protect another sector? start sector protection data = 01h? plscnt = 25? device failed remove v id from a 9 completed remove v id from a 9 write reset command ( a 1 = v ih , a 0 = v il , oe = v id , a 9 = v id a 6 = ce = v il , reset = v ih ( a 19, a 18 , a 17 , a 16, write reset command addr. = sa, a 6 = v il )* a 0 = v il , a 1 = v ih a 15 , a 14 , a 13 , a 12 )
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 51 (6) temporary sector unprotection algorithm *1 : all protected sectors are unprotected. *2 : all previously protected sectors are protected once again. reset = v id *1 perform erase or program operations reset = v ih start temporary sector unprotection completed *2
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 52 (7) embedded programming algorithm for fast mode notes : ? the sequence is applied for 16 mode. ? the addresses differ from 8 mode. yes no 555h/aah verify data? start fast mode algorithm 555h/20h 2aah/55h xxxxh/a0h program address/program data data polling last address ? programming completed xxxxh/90h xxxxh/f0h increment address yes no set fast mode in fast program reset fast mode
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 53 (8) extended sector protect algorithm to setup sector protect yes no time out 150 s reset = v id no data = 01h? start extended sector plscnt = 25? read from sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) to sector protect write 60h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) wait to 4 s protect entry? write xxxh/60h plscnt = 1 to verify sector protect write 40h to sector address (a 0 = v il , a 1 = v ih , a 6 = v il ) protect other sector ? no remove v id from reset write reset command increment plscnt remove v id from reset write reset command yes setup next sector address yes device is operating in temporary sector unprotect mode yes fast mode algorithm device failed sector protection completed no
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 54 ordering information mbm29lv160 device number/description mbm29lv160 16 mega-bit (2m 8-bit or 1m 16-bit) cmos flash memory 3.0 v-only read, write, and erase boot code sector architecture t = top sector b = bottom sector t-80 pftn package type pftn = 48-pin thin small outline package (tsop (1) ) normal bend pftr = 48-pin thin small outline package (tsop (1) ) reverse bend pcv = 48-pin c- leaded small outline package (csop) pbt- sf2= 48-pin fine pitch ball grid array package (fbga:bga-48p-m13) speed option see product selector guide
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 55 part no. package access time (ns) sector architecture mbm29lv160t-80pftn mbm29lv160t-90pftn mbm29lv160t-12pftn 48-pin plastic tsop(1) (fpt-48p-m19) (normal bend) 80 90 120 top sector mbm29lv160t-80pftr mbm29lv160t-90pftr mbm29lv160t-12pftr 48-pin plastic tsop(1) (fpt-48p-m20) (reverse bend) 80 90 120 mbm29lv160t-80pcv mbm29lv160t-90pcv mbm29lv160t-12pcv 48-pin plastic csop (lcc-48p-m03) 80 90 120 mbm29lv160t-80pbt mbm29lv160t-90pbt mbm29lv160t-12pbt 48-ball plastic fbga (bga-48p-m13) 80 90 120 mbm29lv160b-80pftn MBM29LV160B-90PFTN mbm29lv160b-12pftn 48-pin plastic tsop(1) (fpt-48p-m19) (normal bend) 80 90 120 bottom sector mbm29lv160b-80pftr mbm29lv160b-90pftr mbm29lv160b-12pftr 48-pin plastic tsop(1) (fpt-48p-m20) (reverse bend) 80 90 120 mbm29lv160b-80pcv mbm29lv160b-90pcv mbm29lv160b-12pcv 48-pin plastic csop (lcc-48p-m03) 80 90 120 mbm29lv160b-80pbt mbm29lv160b-90pbt mbm29lv160b-12pbt 48-ball plastic fbga (bga-48p-m13) 80 90 120
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 56 package dimensions (continued) 48-pin plastic tsop (1) (fpt-48p-m19) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. ? .003 +.001 ? 0.08 +0.03 .007 0.17 "a" (stand off height) 0.10(.004) (mounting height) (.472 .008) 12.00 0.20 lead no. 48 25 24 1 (.004 .002) 0.10(.004) m 1.10 +0.10 ? 0.05 +.004 ? .002 .043 0.10 0.05 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48029s-c-6-7 c 0~8 ? 0.25(.010) 0.50(.020) 0.60 0.15 (.024 .006) details of "a" part * *
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 57 (continued) 48-pin plastic tsop (1) (fpt-48p-m20) note 1) * : values do not include resin protrusion. resin protrusion and gate protrusion are + 0.15 (.006) max (each side) . note 2) pins width and pins thickness include plating thickness. note 3) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. ? .003 +.001 .007 ? 0.08 +0.03 0.17 "a" (stand off height) (.004 .002) 0.10 0.05 0.10(.004) (mounting height) 12.00 0.20(.472 .008) lead no. 48 25 24 1 0.10(.004) m 1.10 +0.10 ? 0.05 +.004 ? .002 .043 (.009 .002) 0.22 0.05 (.787 .008) 20.00 0.20 (.724 .008) 18.40 0.20 index 2003 fujitsu limited f48030s-c-6-7 c 0~8 ? 0.25(.010) 0.60 0.15 (.024 .006) details of "a" part * * 0.50(.020)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 58 (continued) 48-pin plastic csop (lcc-48p-m03) note 1) *1 : resin protrusion. (each side : + 0.15 (.006) max) . note 2) *2 : these dimensions do not include resin protrusion. note 3) pins width includes plating thickness. note 4) pins width do not include tie bar cutting remainder. dimensions in mm (inches) note : the values in parentheses are reference values. c 2003 fujitsu limited c48056s-c-2-2 10.000.10(.394.004) 0.08(.003) 9.20(.362)ref 1 24 25 48 index index 9.500.10 (.374.004) 10.000.20 (.394.008) "a" 0.220.035 (.009.001) .002 ?.0 +.002 ?0 +0.05 0.05 0.950.05(.037.002) (mounting height) (stand off) 0.65(.026) 1.15(.045) details of "a" part 0?~10? lead no. * 2 * 1 0.40(.016)
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 59 (continued) 48-ball plastic fbga (bga-48p-m13) dimensions in mm (inches) note : the values in parentheses are reference values. c 2001 fujitsu limited b48013s-c-3-2 9.000.20(.354.008) 0.380.10(.015.004) (stand off) (mounting height) 8.000.20 (.315.008) 0.10(.004) 0.80(.031)typ 5.60(.220) 4.00(.157) 48-?0.450.10 (48-?.018.004) m ?0.08(.003) index h g fed c ba 6 5 4 3 2 1 c0.25(.010) .041 ?.004 +.006 ?0.10 +0.15 1.05
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 60 memo
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 61 memo
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 62 memo
retired product y ds05-20846-7e_july 26, 2007 mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 63 revision history revision ds05-20846-7e july 26, 2007 the following comment is added. this product has been retired and is not reco mmended for new designs. availability of this document is retained for reference and historical purposes only.
mbm29lv160t -80/-90/-12 /mbm29lv160b -80/-90/-12 retired product y ds05-20846-7e_july 26, 2007 fujitsu limited for further information please contact: japan fujitsu limited marketing division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3353 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94088-3470, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fme.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fmal.fujitsu.com/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ f0306 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to c onsult with fujitsu sales representatives before ordering. the information, such as descrip tions of function and application circuit examples, in this document are presented solely for the purpose of reference to show exam ples of operations and uses of fujitsu semiconductor device; fujitsu does not warrant proper operation of the device with respect to use based on such information. when you devel op equipment incorporating the device based on such inform ation, you must assume any responsibility arising out of such use of the information. fujitsu assumes no liability for any dama ges whatsoever arising out of the use of the information. any information in this documen t, including descriptions of function and schematic diagrams, sh all not be construed as license of the use or exercise of any intellectual propert y right, such as patent right or copyright, or any ot her right of fujitsu or any third party or does fujitsu warrant non-in fringement of any third-party?s intellectual property right or ot her right by using such information. fujitsu assumes no liability for any infringement of the intellectual property rights or other rights of third parties which would result from the use of information contained herein. the products described in this document are designed, developed and manufactured as c ontemplated for gene ral use, including without limitation, ordinary industrial us e, general office use, personal use, and household use, but are not designed, developed and manufactured as contemplated (1) for use accompanying fatal risks or dangers that, unless extrem ely high safety is secured, could have a serious effect to the public, and could lead directly to death, personal injury, severe physical damage or othe r loss (i.e., nuclear reaction control in nuclear facility, ai rcraft flight cont rol, air traffic control, mass transpor t control, medical life support system, missile launch control in weapon system), or (2) for use requiring extremely high reliability (i.e., su bmersible repeater and artificial satellite). please note that fujitsu will not be liab le against you and/or any third party for any claims or da mages arising in connection with above-mentioned uses of the products. any semiconductor devices have an inherent chance of failure. you must protect against injury, dama ge or loss from such failures by incorporating safety design meas ures into your facility and equipment such as redundancy, fi re protection, and prevention of over-current levels and othe r abnormal operating conditions. if any products described in th is document repr esent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japane se government will be required for export of those products from japan.

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